My next motherboard

WOW .. wee!! WOWwee!! you da man!! you da NEW man!! not old man! da new man!! new sheriff in town he goes by name of DA PLUMBER! :D dis aint ol' man .. dis da new mang!! DA PLUMBER! whew hoo! whew!! heavy heavy chevy whee hoo. T- THREE .. 20 mEGS ..whoo wee thats heavy!:p
 
Quote from theplumber:

The steamthru technology may be what your looking for. I posted this 1 year ago. The nForce 3 pro is what I use with dual 248 Opterons, works like a dream http://www.nvidia.com/page/nforce3.html go to the relevent links pdf. I have 3 updating ANN's about every half hour crunching 20 megs each while running 3 charting programs on a T-3 line with not one glitch since I built it. Also the next nForce coming, the 250 I think, will have PCI-X so you may want to wait for that one and one for 4 way as well.
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Fasnicating.

When I first saw your link, my first thought was, "what does a graphics card have to do with the price of TCP/IP in china?"

But then I started reading, and this thing is talking about "Enterprise Class Networking" :eek:

http://www.nvidia.com/object/feature_network.html

So now I am really confused. Is this thing, nForce3, a graphics card, or some sort of chipset used on NICs and graphics cards? I can't make heads or tails of what this article is trying to tell me.

Either way, thanks for the link...


nitro :confused:
 
Quote from nitro:
The first part makes sense. However, I don't follow the second. The memory footprint of the program has nothing to do with the cache hit on the CPUs internal cache(s)?
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I mean the memory footprint of the code which is your processing bottleneck (inner loop). If this code is using 99% of CPU while mostly accessing less than 512KB of memory, then any cache larger than 512KB won't give you much improvement. Smaller caches would definitely reduce performance.

Even though your program accesses several GB of memory over long intervals, over short intervals it uses much less, often with definite patterns which can be optimized for reuse.

Cache optimization can be dramatic. I recently wrote some backtesting code that benchmarks at 100M ES ticks / second on a single 2.8 GHz P4 processor. Before optimization for locality this code ran about 20 times slower.

Try these for more info:

http://engineering.dartmouth.edu/~engs116/lectures/engs 116 lecture 13-03f.ppt

http://www.gdconf.com/archives/2003/Ericson_Christer.ppt
 
Very cool.

I really like the second article. Thanks.

nitro :cool:
Quote from prophet:

I mean the memory footprint of the code which is your processing bottleneck (inner loop). If this code is using 99% of CPU while mostly accessing less than 512KB of memory, then any cache larger than 512KB won't give you much improvement. Smaller caches would definitely reduce performance.

Even though your program accesses several GB of memory over long intervals, over short intervals it uses much less, often with definite patterns which can be optimized for reuse.

Cache optimization can be dramatic. I recently wrote some backtesting code that benchmarks at 100M ES ticks / second on a single 2.8 GHz P4 processor. Before optimization for locality this code ran about 20 times slower.

Try these for more info:

http://engineering.dartmouth.edu/~engs116/lectures/engs 116 lecture 13-03f.ppt

http://www.gdconf.com/archives/2003/Ericson_Christer.ppt
More...
 
Quote from nitro:

Fasnicating.

When I first saw your link, my first thought was, "what does a graphics card have to do with the price of TCP/IP in china?"

But then I started reading, and this thing is talking about "Enterprise Class Networking" :eek:

http://www.nvidia.com/object/feature_network.html

So now I am really confused. Is this thing, nForce3, a graphics card, or some sort of chipset used on NICs and graphics cards? I can't make heads or tails of what this article is trying to tell me.

Either way, thanks for the link...


nitro :confused:
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the nforce chips are the north bridge and south bridge chips
 
Quote from fxtrading:

the nforce chips are the north bridge and south bridge chips
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Aaaaaaaaaaaaaaaahhhh!

LOL. AMD bought this technology from nVidia an renamed it?

nitro
 
Quote from nitro:

Aaaaaaaaaaaaaaaahhhh!

LOL. AMD bought this technology from nVidia an renamed it?

nitro
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the motherboard manufacturers license the chips - but it looks like nvidia teamed up with amd to make sure the two where compatible at 64 and 32 bits

heres a list of motherboards with nforce chip sets
http://www.nvidia.com/object/motherboards.html


the propaganda from nvidia

The NVIDIA nForce3 MCPs complement the newest AMD 64-bit processors, providing optimized operation in all three modes. System designers can take advantage of the AMD-NVIDIA combination today to build optimized 32-bit compatible systems that also get the most out of 64-bit operating systems and applications.


features of nforce3 chips

http://www.nvidia.com/page/pg_20030917982606.html
 
speaking of amd 64 - the new unreal tournament 2004 will have a 64 bit amd linux dedicated server port.

well im off to play the demo
 
Quote from nitro:

No!

The new (Quad only?) opteron boards have dual channel PCI/X buses! That is the whole point! Check out:

http://www.amdboard.com/tyan_s4882_opteron_board.html

Look at "Expansion Slots" - "Two independent PCI-X buses."

However, I do not know how the hardware interacts with the OS on this.

To add to that, I have no idea on what bus the _onboard_ NICs are.

Even in this case, there is probably no way to assure that the NIC's get one PCI-X bus to itself. Ugh, I honestly don't know.

nitro
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I read the link more carefully and the broadcom Gig Nics are on connected to PCI-X Bridge A.

nitro
 
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