A) With the development of new process technologies and advanced packaging solutions, transistor scale and packaging density continue to grow. Today’s AI chips all use 2.5D stacking, 3D stacking, and Chiplet technology. These advancements lead to higher demand for chip test equipment, which also requires increasingly sophisticated test equipment to pinpoint errors.
B)Since the only solution for chip manufacturers is to buy more tools to test chips, test equipment manufacturers have also greatly benefited from this round of AI hype. It is foreseeable that the global revenue of high-performance GPU chip testing equipment may exceed that of smartphone chip testing equipment in the next few years
C)Advanced AI Requires Advanced IC Packaging
Massive parallelism once existed exclusively in the realm of supercomputers, but recent advances in chip technology allow it to now reside on a single IC substrate that integrates literally billions of transistors. One key breakthrough in this area is the emergence of advanced packaging, which allows multiple logic functions to be positioned within very close proximity to each other to maximize speed and minimize energy consumption.
Probing the Inner Limits
Each layer must be functionally verified before going on the advanced package die stack stack, and may include up to 4000 test points called microbumps that lead to data paths, power supplies and ground. Microbump test points are positioned extremely close to each other, often within 45 μm. And each presents a very small probe target, on the order of 25 μm.