Oh baby Touchdown-
I figured it out... This co is a high voltage co namely 48 volt <----- There is a big semi transition in tech to this higher Voltage ability. Converting lower voltage chips to 48 etc. This has been an ongoing tech transition story for 2 years--
But wait- Why Now-?
mpany Profile
Vicor Corporation, together with its subsidiaries, designs, develops, manufactures and markets modular power components and power systems for converting electrical power in the United States and internationally. The company offers a range of brick-format DC-DC converters; complementary components provide AC line rectification, input filtering, power factor correction, and transient protection; and input and output voltage, and output power products, as well as electrical and mechanical accessories. It also provides custom power systems solutions. The company serves independent manufacturers of electronic devices, original equipment manufacturers, and their contract manufacturers in the aerospace and aviation, defense electronics, industrial automation and equipment, instrumentation, test equipment, solid state lighting, telecommunications and networking infrastructure, and vehicles and transportation markets. Vicor Corporation was incorporated in 1981 and is headquartered in Andover, Massachusetts.
It hit me out of the blue-- AI. Duh. AI is going to demand 48 volts<-----
The recent introduction of new clustered AI ASIC processor based supercomputers are pushing the boundaries of power delivery networks to levels that were never imagined just a few years ago. With current levels approaching 100 kiloamps/ASIC cluster, innovation is needed across power system architectures, topologies, control systems and packaging to deliver such high currents. Because of the escalating power levels, 48V power delivery is essential. Furthermore, tightly packed processor clusters limit the feasibility of lateral power delivery, rendering a new approach necessary.
Vicor 48V direct-to-load (<1V) Factorized Power Architecture (FPA™) is a major departure from the common 48V intermediate bus architecture (IBA) consisting of an intermediate bus converter followed by multiphase PoL regulators. FPA uniquely addresses each of the power delivery challenges facing clustered processor systems with innovative solutions and also enables vertical power delivery (VPD), which is essential to provide high currents to such systems.
Clustered power delivery challenges
Clustered ASICs are tightly packed to achieve the high-speed bandwidth required to achieve the teraflops of processing performance required for AI training workloads such as autonomous driving. Each processor in the cluster can itself require 600 to 1000 amps, which for even single-processor accelerator cards presents a power delivery challenge with significant PCB or substrate impedance losses if the VR placement is not physically close to the processor power pins.
Additionally, the rapid advancements in artificial intelligence (AI) are being enabled by GPUs and specialized AI processors utilizing silicon process nodes at 7nm, 5nm and soon, 3nm. Nominal core operating voltages at these process nodes are currently between 0.75 and 0.85V. To meet the performance workloads that AI demands, GPUs and processors are mounted on accelerator cards which are then clustered into a server rack based system with 4, or 8 cards per rack for data centers and high performance computers. However recent introductions from Cerebras and Tesla have shown an alternate approach of clustering the AI ASICs themselves which enables extremely fast, high-density supercomputers but presents additional significant power delivery and thermal management/cooling challenges.
For power delivery, the ASIC/GPU cluster leaves no room for lateral power delivery as in single- or dual-processor AI cards and the high-speed I/O used is extremely sensitive to high-current switching noise as is present with hard-switching multiphase buck regulators. Moving the hard-switching multiphase VR even closer to the processor also brings the associated VR noise with it which further compounds the number challenge of designing a PDN sufficient for the noise-sensitive I/O. At a typical design value of 40 – 60A/phase, the number of discrete phases needed to deliver high peak currents (>1500A per core in many cases) can easily exceed 30 phases per AI ASIC or GPU, a number that is difficult, if not impossible, to achieve with lateral power delivery.
I figured it out... This co is a high voltage co namely 48 volt <----- There is a big semi transition in tech to this higher Voltage ability. Converting lower voltage chips to 48 etc. This has been an ongoing tech transition story for 2 years--
But wait- Why Now-?
mpany Profile
Vicor Corporation, together with its subsidiaries, designs, develops, manufactures and markets modular power components and power systems for converting electrical power in the United States and internationally. The company offers a range of brick-format DC-DC converters; complementary components provide AC line rectification, input filtering, power factor correction, and transient protection; and input and output voltage, and output power products, as well as electrical and mechanical accessories. It also provides custom power systems solutions. The company serves independent manufacturers of electronic devices, original equipment manufacturers, and their contract manufacturers in the aerospace and aviation, defense electronics, industrial automation and equipment, instrumentation, test equipment, solid state lighting, telecommunications and networking infrastructure, and vehicles and transportation markets. Vicor Corporation was incorporated in 1981 and is headquartered in Andover, Massachusetts.
It hit me out of the blue-- AI. Duh. AI is going to demand 48 volts<-----
The recent introduction of new clustered AI ASIC processor based supercomputers are pushing the boundaries of power delivery networks to levels that were never imagined just a few years ago. With current levels approaching 100 kiloamps/ASIC cluster, innovation is needed across power system architectures, topologies, control systems and packaging to deliver such high currents. Because of the escalating power levels, 48V power delivery is essential. Furthermore, tightly packed processor clusters limit the feasibility of lateral power delivery, rendering a new approach necessary.
Vicor 48V direct-to-load (<1V) Factorized Power Architecture (FPA™) is a major departure from the common 48V intermediate bus architecture (IBA) consisting of an intermediate bus converter followed by multiphase PoL regulators. FPA uniquely addresses each of the power delivery challenges facing clustered processor systems with innovative solutions and also enables vertical power delivery (VPD), which is essential to provide high currents to such systems.
Clustered power delivery challenges
Clustered ASICs are tightly packed to achieve the high-speed bandwidth required to achieve the teraflops of processing performance required for AI training workloads such as autonomous driving. Each processor in the cluster can itself require 600 to 1000 amps, which for even single-processor accelerator cards presents a power delivery challenge with significant PCB or substrate impedance losses if the VR placement is not physically close to the processor power pins.
Additionally, the rapid advancements in artificial intelligence (AI) are being enabled by GPUs and specialized AI processors utilizing silicon process nodes at 7nm, 5nm and soon, 3nm. Nominal core operating voltages at these process nodes are currently between 0.75 and 0.85V. To meet the performance workloads that AI demands, GPUs and processors are mounted on accelerator cards which are then clustered into a server rack based system with 4, or 8 cards per rack for data centers and high performance computers. However recent introductions from Cerebras and Tesla have shown an alternate approach of clustering the AI ASICs themselves which enables extremely fast, high-density supercomputers but presents additional significant power delivery and thermal management/cooling challenges.
For power delivery, the ASIC/GPU cluster leaves no room for lateral power delivery as in single- or dual-processor AI cards and the high-speed I/O used is extremely sensitive to high-current switching noise as is present with hard-switching multiphase buck regulators. Moving the hard-switching multiphase VR even closer to the processor also brings the associated VR noise with it which further compounds the number challenge of designing a PDN sufficient for the noise-sensitive I/O. At a typical design value of 40 – 60A/phase, the number of discrete phases needed to deliver high peak currents (>1500A per core in many cases) can easily exceed 30 phases per AI ASIC or GPU, a number that is difficult, if not impossible, to achieve with lateral power delivery.
